Motivation


The motivation for this webpage is to share my work on:

    - PDVL: An aspect and transaction oriented Programming, Design and Verification Language,

    - SHP: System Hyper Pipelining,

    - as well as ASIC testing related projects (DFT).

News:


I will give a talk on "Combining Simulation And FPGA Based Verification To An Affordable And Ultra-Fast Multi-Billion-Gate Verification System" at the Rapid System Prototyping Workshop in October 2019, New York, USA


I will give a talk on "An RTL ATPG Flow Using the Gate Inherent Fault (GIF) Model Applied On Non-, Standard- And Random-Access-Scan (RAS)" 
at the Euromicro DSD conference in August 2019, Kallithea, Greece


Latest IEEE paper on PDVL and "Dynamic Inside-Out Verification Using Inverse Transactions in TLM" is now online: https://ieeexplore.ieee.org/document/8524048


I will give a talk on PDVL and "Dynamic Inside-Out Verification Using Inverse Transactions in TLM" at the FDL-conference in Munich, http://www.fdl-conference.org



last modified: 2019/Aug/1