The motivation for
this webpage is to share my work on:
- PDVL: An aspect and transaction oriented Programming, Design
and Verification Language,
- SHP: System Hyper Pipelining,
- as well
as ASIC testing
RISC-V based Arduissimo
I will give a talk on
Simulation and FPGA Based Verification to an Afforfable and Ultra-Fast
Multi-Billion-Gate Verification System" at the Rapid System Prototyping Workshop
in October 2019,
New York, USA.
I will give a talk on "An RTL ATPG Flow Using the Gate Inherent Fault
(GIF) Model Applied on Non-, Standard- And Random-Access-Scan
DSD conference in August 2019,
Latest IEEE paper
"Dynamic Inside-Out Verification Using Inverse Transactions in TLM" is
now online: https://ieeexplore.ieee.org/document/8524048.
I will give a talk on PDVL and
"Dynamic Inside-Out Verification Using Inverse Transactions in TLM" at
the FDL-conference in Munich, http://www.fdl-conference.org.